Dijital Saat Uygulamasının Nexys 4 Kartı Üzerinde Gerçeklenmesi

Aşağıda ayarlanabilir dijital saat uygulamasının Nexys 4 kartı üzerinde gerçeklenmesine ait kodlar ve videolar gösterilmiştir. digital_clock.vhd dosyası saat kontrol işlemlerinin yapıldığı ana modüldür. Saniye ve dakika ayarları için min_sec_digit_cntrl.vhd  modülü tasarlanmıştır. Saat ayarları için ise hour_digit_cntrl.vhd modülü tasarlanmıştır.

Digital Saat tasarımında her bir birimin ayarlanabilmesi sağlanmıştır. Saatin çalışmasına ilişkin video aşağıdadır.

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5.  
  6. entity digital_clock is
  7.     generic(
  8.         SYS_FREQ : integer := 100_000_000
  9.     );
  10.     Port(
  11.         in_clk : in std_logic;
  12.         in_rst : in std_logic;
  13.         in_set : in std_logic;
  14.         in_chng_seg : in std_logic;
  15.         in_inc : in std_logic;
  16.         out_seg : out std_logic_vector(7 downto 0);
  17.         out_seg_leds : out std_logic_vector(7 downto 0)          
  18.     );
  19. end digital_clock;
  20.  
  21. architecture Behavioral of digital_clock is
  22.  
  23.  
  24.     component hour_digit_cntrl
  25.     Port (
  26.         in_clk : in std_logic;
  27.         in_rst : in std_logic;
  28.         in_pulse : in std_logic;
  29.         in_inc_right : in std_logic;
  30.         in_inc_left : in std_logic;
  31.         out_right_digit : out std_logic_vector(3 downto 0);
  32.         out_left_digit : out std_logic_vector(3 downto 0)
  33.     );
  34.     end component;
  35.    
  36.     component min_sec_digit_cntrl
  37.     Generic(
  38.         DIGIT_SIZE : integer := 10
  39.     );
  40.     Port (
  41.         in_clk : in std_logic;
  42.         in_rst : in std_logic;
  43.         in_pulse : in std_logic;
  44.         in_inc : in std_logic;
  45.         out_digit : out std_logic_vector(3 downto 0);
  46.         out_pulse : out std_logic      
  47.     ); 
  48.     end component;
  49.    
  50.     component bcd2seven_segment
  51.     Port (
  52.         in_bcd : in std_logic_vector(3 downto 0);
  53.         out_seven_segment : out std_logic_vector(7 downto 0)
  54.     );
  55.     end component;
  56.    
  57.     component pulse_generator
  58.     generic(
  59.         FREQ : integer := 100_000_000
  60.     );
  61.     Port (
  62.         in_clk : in std_logic;
  63.         in_rst : in std_logic;
  64.         out_sec_pulse : out std_logic
  65.     );
  66.     end component;
  67.    
  68.     type t_Time_Digits is array (0 to 5) of std_logic_vector(3 downto 0);
  69.     signal r_Time_Digits : t_Time_Digits := (others=>(others => '0'));
  70.    
  71.     signal r_bcd : std_logic_vector(3 downto 0) := (others => '0');
  72.     signal r_seg_leds : std_logic_vector(7 downto 0) := (others => '0');
  73.     signal r_seg : std_logic_vector(5 downto 0) := "011111";
  74.     signal r_seg_cnt : std_logic_vector(2 downto 0) := (others => '0');
  75.     signal r_seg_pulse : std_logic := '0';
  76.     --
  77.     signal r_sec_pulse : std_logic := '0';
  78.     signal r_sec_right_pulse : std_logic := '0';
  79.     signal r_sec_left_pulse : std_logic := '0';
  80.     signal r_min_right_pulse : std_logic := '0';
  81.     signal r_min_left_pulse : std_logic := '0';
  82.     --
  83.     signal r_set : std_logic := '0';
  84.     signal r_set_chk : std_logic_vector(5 downto 0) := "011111";
  85.     signal r_set_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
  86.     signal r_set_cnt : integer := 0;
  87.     signal r_set_stts : std_logic := '0';
  88.    
  89.    
  90.     signal r_chng_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
  91.     signal r_set_seg : std_logic_vector(2 downto 0) := (others=> '0');
  92.    
  93.     signal r_inc_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
  94.     signal r_inc_seg : std_logic_vector(5 downto 0) := (others=> '0');
  95.    
  96.     function f_set_shift(r_seg : std_logic_vector(5 downto 0) ; r_set_stts : std_logic; r_set_seg : std_logic_vector(2 downto 0) ) return std_logic_vector is
  97.         variable v_seg : std_logic_vector(5 downto 0);
  98.     begin
  99.         v_seg := r_seg;
  100.         if v_seg(conv_integer(r_set_seg)) = '0' then
  101.             v_seg(conv_integer(r_set_seg)) := r_set_stts;
  102.         end if;
  103.         return ("11" & v_seg);
  104.     end f_set_shift;
  105.  
  106. begin
  107.  
  108.     out_seg_leds <= r_seg_leds;
  109.     out_seg <= f_set_shift(r_seg, r_set_stts, r_set_seg);
  110.    
  111.     process(in_clk, in_rst)
  112.     begin
  113.         if in_rst = '1' then
  114.             r_set_cnt <= 0;
  115.             r_set_stts <= '0';
  116.         elsif rising_edge(in_clk) then
  117.             if r_set = '1' then
  118.                 if r_set_cnt = (SYS_FREQ / 2) - 1 then
  119.                     r_set_cnt <= 0;
  120.                     r_set_stts <= not r_set_stts;
  121.                 else
  122.                     r_set_cnt <= r_set_cnt + 1;
  123.                 end if;
  124.             else
  125.                 r_set_cnt <= 0;
  126.                 r_set_stts <= '0';
  127.             end if;
  128.         end if;
  129.     end process;
  130.    
  131.     process(in_clk, in_rst)
  132.     begin
  133.         if in_rst = '1' then
  134.             r_inc_seg <= (others => '0');
  135.         elsif rising_edge(in_clk) then
  136.             r_inc_seg <= (others => '0');
  137.             if r_inc_cntrl(2 downto 1) = "01" then
  138.                 r_inc_seg(5 - conv_integer(r_set_seg)) <= '1';
  139.             end if;            
  140.         end if;
  141.     end process;       
  142.        
  143.     process(in_clk, in_rst)
  144.     begin
  145.         if in_rst = '1' then           
  146.             r_inc_cntrl <= (others=> '0');
  147.         elsif rising_edge(in_clk) then
  148.             r_inc_cntrl <= r_inc_cntrl(1 downto 0) &  in_inc;
  149.         end if;
  150.     end process;
  151.    
  152.     process(in_clk, in_rst)
  153.     begin
  154.         if in_rst = '1' then
  155.             r_seg <= "011111";
  156.             r_set_chk <= "111111"; 
  157.         elsif rising_edge(in_clk) then
  158.             if r_seg_pulse = '1' then
  159.                 r_seg <= r_seg(4 downto 0) & r_seg(5);
  160.  
  161.             end if;        
  162.         end if;
  163.     end process;
  164.  
  165.     process(in_clk, in_rst)
  166.     begin
  167.         if in_rst = '1' then
  168.             r_set_seg <= (others => '0');
  169.         elsif rising_edge(in_clk) then
  170.             if r_chng_cntrl(2 downto 1) = "01" then
  171.                 if r_set_seg = 5 then
  172.                     r_set_seg <= (others => '0');
  173.                 else
  174.                     r_set_seg <= r_set_seg + 1;
  175.                 end if;
  176.             end if;            
  177.         end if;
  178.     end process;       
  179.        
  180.     process(in_clk, in_rst)
  181.     begin
  182.         if in_rst = '1' then           
  183.             r_chng_cntrl <= (others=> '0');
  184.         elsif rising_edge(in_clk) then
  185.             r_chng_cntrl <= r_chng_cntrl(1 downto 0) &  in_chng_seg;
  186.         end if;
  187.     end process;   
  188.    
  189.     process(in_clk, in_rst)
  190.     begin
  191.         if in_rst = '1' then
  192.             r_seg_cnt <= (others => '0');
  193.             r_bcd <= (others => '0');
  194.                
  195.         elsif rising_edge(in_clk) then
  196.             if r_seg_pulse = '1' then
  197.                 r_bcd <= r_Time_Digits(5 - conv_integer(r_seg_cnt));
  198.                 if r_seg_cnt = 5 then
  199.                     r_seg_cnt <= (others => '0');
  200.                 else
  201.                     r_seg_cnt <= r_seg_cnt + 1;
  202.                 end if;
  203.             end if;        
  204.         end if;
  205.     end process;
  206.    
  207.     process(in_clk, in_rst)
  208.     begin
  209.         if in_rst = '1' then
  210.             r_set <= '0';
  211.         elsif rising_edge(in_clk) then
  212.             if r_set_cntrl(2 downto 1) = "01" then
  213.                 r_set <= not r_set;
  214.             end if;            
  215.         end if;
  216.     end process;       
  217.        
  218.     process(in_clk, in_rst)
  219.     begin
  220.         if in_rst = '1' then           
  221.             r_set_cntrl <= (others=> '0');
  222.         elsif rising_edge(in_clk) then
  223.             r_set_cntrl <= r_set_cntrl(1 downto 0) &  in_set;
  224.         end if;
  225.     end process;   
  226.    
  227.    
  228.     bcd2seven_segment_map : bcd2seven_segment
  229.     Port  map(
  230.         in_bcd => r_bcd,
  231.         out_seven_segment => r_seg_leds
  232.     );
  233.  
  234.     hour_digit_cntrl_map : hour_digit_cntrl
  235.     Port map (
  236.         in_clk => in_clk,
  237.         in_rst => in_rst,
  238.         in_pulse => r_min_left_pulse,
  239.         in_inc_right => r_inc_seg(1),
  240.         in_inc_left => r_inc_seg(0),
  241.         out_right_digit => r_Time_Digits(1),
  242.         out_left_digit => r_Time_Digits(0)
  243.     );
  244.    
  245.     min_left_digit : min_sec_digit_cntrl
  246.     Generic map(
  247.         DIGIT_SIZE => 6
  248.     )
  249.     Port map(
  250.         in_clk => in_clk,
  251.         in_rst => in_rst,
  252.         in_pulse => r_min_right_pulse,
  253.         in_inc => r_inc_seg(2),
  254.         out_digit => r_Time_Digits(2),
  255.         out_pulse => r_min_left_pulse
  256.     ); 
  257.  
  258.     min_right_digit : min_sec_digit_cntrl
  259.     Generic map(
  260.         DIGIT_SIZE => 10
  261.     )
  262.     Port map(
  263.         in_clk => in_clk,
  264.         in_rst => in_rst,
  265.         in_pulse => r_sec_left_pulse,
  266.         in_inc => r_inc_seg(3),
  267.         out_digit => r_Time_Digits(3),
  268.         out_pulse => r_min_right_pulse
  269.     ); 
  270.  
  271.     sec_left_digit : min_sec_digit_cntrl
  272.     Generic map(
  273.         DIGIT_SIZE => 6
  274.     )
  275.     Port map(
  276.         in_clk => in_clk,
  277.         in_rst => in_rst,
  278.         in_pulse => r_sec_right_pulse,
  279.         in_inc => r_inc_seg(4),
  280.         out_digit => r_Time_Digits(4),
  281.         out_pulse => r_sec_left_pulse
  282.     ); 
  283.  
  284.     sec_right_digit : min_sec_digit_cntrl
  285.     Generic map(
  286.         DIGIT_SIZE => 10
  287.     )
  288.     Port map(
  289.         in_clk => in_clk,
  290.         in_rst => in_rst,
  291.         in_pulse => r_sec_pulse,
  292.         in_inc => r_inc_seg(5),
  293.         out_digit => r_Time_Digits(5),
  294.         out_pulse => r_sec_right_pulse
  295.     ); 
  296.    
  297.     seg_pulse_map : pulse_generator
  298.     generic map(
  299.         FREQ => 10_000
  300.     )
  301.     Port map (
  302.         in_clk => in_clk,
  303.         in_rst => in_rst,
  304.         out_sec_pulse => r_seg_pulse
  305.     ); 
  306.    
  307.     one_second_pulse_map : pulse_generator
  308.     generic map(
  309.         FREQ => SYS_FREQ
  310.     )
  311.     Port map (
  312.         in_clk => in_clk,
  313.         in_rst => in_rst,
  314.         out_sec_pulse => r_sec_pulse
  315.     );
  316.  
  317. end Behavioral;
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity pulse_generator is
  5.     generic(
  6.         FREQ : integer := 100_000_000
  7.     );
  8.     Port (
  9.         in_clk : in std_logic;
  10.         in_rst : in std_logic;
  11.         out_sec_pulse : out std_logic
  12.     );
  13. end pulse_generator;
  14.  
  15. architecture Behavioral of pulse_generator is
  16.  
  17.     signal r_sec_pulse : std_logic := '0';
  18.     signal r_cnt : integer := 0;
  19.    
  20. begin
  21.  
  22.     out_sec_pulse <= r_sec_pulse;
  23.  
  24.     process(in_clk, in_rst)
  25.     begin
  26.         if in_rst = '1' then
  27.             r_cnt<= 0;
  28.             r_sec_pulse <= '0';
  29.            
  30.         elsif rising_edge(in_clk) then
  31.             if r_cnt = FREQ - 1 then
  32.                 r_sec_pulse <= '1';
  33.                 r_cnt<= 0;
  34.             else
  35.                 r_sec_pulse <= '0';
  36.                 r_cnt <= r_cnt + 1;        
  37.             end if;
  38.            
  39.         end if;
  40.     end process;
  41.  
  42. end Behavioral;
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5.  
  6. entity min_sec_digit_cntrl is
  7.     Generic(
  8.         DIGIT_SIZE : integer := 10
  9.     );
  10.     Port (
  11.         in_clk : in std_logic;
  12.         in_rst : in std_logic;
  13.         in_pulse : in std_logic;
  14.         in_inc : in std_logic;
  15.         out_digit : out std_logic_vector(3 downto 0);
  16.         out_pulse : out std_logic  
  17.     );
  18. end min_sec_digit_cntrl;
  19.  
  20. architecture Behavioral of min_sec_digit_cntrl is
  21.  
  22.     signal r_digit : std_logic_vector(3 downto 0) := (others => '0');
  23.     signal r_pulse : std_logic := '0';
  24.  
  25. begin
  26.  
  27.     out_digit <= r_digit;
  28.     out_pulse <= r_pulse;
  29.    
  30.     process(in_clk, in_rst)
  31.     begin
  32.         if in_rst = '1' then
  33.             r_digit <= (others => '0');
  34.             r_pulse <= '0';
  35.         elsif rising_edge(in_clk) then
  36.             r_pulse <= '0';
  37.             if in_pulse = '1' then
  38.                 if r_digit = DIGIT_SIZE - 1 then
  39.                     r_pulse <= '1';
  40.                     r_digit <= (others => '0');
  41.                 else
  42.                     r_digit <= r_digit + 1;
  43.                 end if;                            
  44.             end if;
  45.            
  46.             if in_inc = '1' then
  47.                 if r_digit = DIGIT_SIZE - 1 then
  48.                     r_digit <= (others => '0');
  49.                 else
  50.                     r_digit <= r_digit + 1;
  51.                 end if;
  52.             end if;
  53.         end if;
  54.     end process;
  55.  
  56. end Behavioral;
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5.  
  6. entity hour_digit_cntrl is
  7.     Port (
  8.         in_clk : in std_logic;
  9.         in_rst : in std_logic;
  10.         in_pulse : in std_logic;
  11.         in_inc_right : in std_logic;
  12.         in_inc_left : in std_logic;
  13.         out_right_digit : out std_logic_vector(3 downto 0);
  14.         out_left_digit : out std_logic_vector(3 downto 0)
  15.     );
  16. end hour_digit_cntrl;
  17.  
  18. architecture Behavioral of hour_digit_cntrl is
  19.  
  20.     signal r_right_digit : std_logic_vector(3 downto 0);
  21.     signal r_left_digit : std_logic_vector(3 downto 0);
  22.  
  23. begin
  24.    
  25.     out_right_digit <= r_right_digit;
  26.     out_left_digit <= r_left_digit;
  27.  
  28.     process(in_clk, in_rst)
  29.     begin
  30.         if in_rst = '1' then
  31.             r_right_digit <= (others => '0');
  32.             r_left_digit <= (others => '0');
  33.         elsif rising_edge(in_clk) then
  34.             if in_pulse = '1' then
  35.                 if (r_left_digit /= 2 and r_right_digit = 9) or
  36.                     (r_left_digit = 2 and r_right_digit = 3) then      
  37.                     r_right_digit <= (others => '0');
  38.                     if r_left_digit = 2 then
  39.                         r_left_digit <= (others => '0');
  40.                     else
  41.                         r_left_digit <= r_left_digit + 1;
  42.                     end if;
  43.                 else
  44.                     r_right_digit <= r_right_digit + 1;
  45.                 end if;                            
  46.             end if;
  47.            
  48.             if in_inc_right = '1' then
  49.                 if (r_left_digit /= 2 and r_right_digit = 9) or
  50.                     (r_left_digit = 2 and r_right_digit = 3) then      
  51.                     r_right_digit <= (others => '0');
  52.                 else
  53.                     r_right_digit <= r_right_digit + 1;
  54.                 end if;
  55.             end if;
  56.            
  57.             if in_inc_left = '1' then
  58.                 if r_left_digit = 2 then
  59.                     r_left_digit <= (others => '0');
  60.                 else
  61.                     r_left_digit <= r_left_digit + 1;
  62.                 end if;
  63.             end if;
  64.         end if;
  65.     end process;
  66.  
  67.  
  68. end Behavioral;
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity bcd2seven_segment is
  5.     Port (
  6.         in_bcd : in std_logic_vector(3 downto 0);
  7.         out_seven_segment : out std_logic_vector(7 downto 0)
  8.     );
  9. end bcd2seven_segment;
  10.  
  11. architecture Behavioral of bcd2seven_segment is
  12.  
  13.     signal r_seven_segment : std_logic_vector(7 downto 0) := (others => '0');
  14.  
  15. begin
  16.  
  17.     out_seven_segment <= r_seven_segment;
  18.  
  19.     process(in_bcd)
  20.     begin
  21.         case in_bcd is
  22.             when "0000" =>
  23.                 r_seven_segment <= "10000001";
  24.             when "0001" =>
  25.                 r_seven_segment <= "11001111";             
  26.             when "0010" =>
  27.                 r_seven_segment <= "10010010";             
  28.             when "0011" =>
  29.                 r_seven_segment <= "10000110";             
  30.             when "0100" =>
  31.                 r_seven_segment <= "11001100";             
  32.             when "0101" =>
  33.                 r_seven_segment <= "10100100";
  34.             when "0110" =>
  35.                 r_seven_segment <= "10100000";
  36.             when "0111" =>
  37.                 r_seven_segment <= "10001111";
  38.             when "1000" =>
  39.                 r_seven_segment <= "10000000";
  40.             when "1001" =>
  41.                 r_seven_segment <= "10000100";
  42.             when others =>
  43.                 r_seven_segment <= "00000000";         
  44.         end case;
  45.     end process;
  46.  
  47.  
  48. end Behavioral;
  1. set_property PACKAGE_PIN E3 [get_ports in_clk]
  2. set_property IOSTANDARD LVCMOS33 [get_ports in_clk]
  3.  
  4. set_property PACKAGE_PIN F15 [get_ports in_rst]
  5. set_property IOSTANDARD LVCMOS33 [get_ports in_rst]
  6.  
  7. set_property PACKAGE_PIN M1 [get_ports {out_seg[7]}]
  8. set_property PACKAGE_PIN L1 [get_ports {out_seg[6]}]
  9. set_property PACKAGE_PIN N4 [get_ports {out_seg[5]}]
  10. set_property PACKAGE_PIN N2 [get_ports {out_seg[4]}]
  11. set_property PACKAGE_PIN N5 [get_ports {out_seg[3]}]
  12. set_property PACKAGE_PIN M3 [get_ports {out_seg[2]}]
  13. set_property PACKAGE_PIN M6 [get_ports {out_seg[1]}]
  14. set_property PACKAGE_PIN N6 [get_ports {out_seg[0]}]
  15.  
  16. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[7]}]
  17. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[6]}]
  18. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[5]}]
  19. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[4]}]
  20. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[3]}]
  21. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[2]}]
  22. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[1]}]
  23. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[0]}]
  24.  
  25.  
  26. set_property PACKAGE_PIN M4 [get_ports {out_seg_leds[7]}]
  27. set_property PACKAGE_PIN L3 [get_ports {out_seg_leds[6]}]
  28. set_property PACKAGE_PIN N1 [get_ports {out_seg_leds[5]}]
  29. set_property PACKAGE_PIN L5 [get_ports {out_seg_leds[4]}]
  30. set_property PACKAGE_PIN L4 [get_ports {out_seg_leds[3]}]
  31. set_property PACKAGE_PIN K3 [get_ports {out_seg_leds[2]}]
  32. set_property PACKAGE_PIN M2 [get_ports {out_seg_leds[1]}]
  33. set_property PACKAGE_PIN L6 [get_ports {out_seg_leds[0]}]
  34.  
  35. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[7]}]
  36. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[6]}]
  37. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[5]}]
  38. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[4]}]
  39. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[3]}]
  40. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[2]}]
  41. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[1]}]
  42. set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[0]}]
  43.  
  44.  
  45. set_property PACKAGE_PIN E16 [get_ports in_set]
  46. set_property PACKAGE_PIN R10 [get_ports in_inc]
  47. set_property IOSTANDARD LVCMOS33 [get_ports in_inc]
  48. set_property IOSTANDARD LVCMOS33 [get_ports in_set]
  49.  
  50. set_property PACKAGE_PIN V10 [get_ports in_chng_seg]
  51. set_property IOSTANDARD LVCMOS33 [get_ports in_chng_seg]
Latest Comments
  1. Rusen

    Helal m ali istersen yapamayacagin birsey yok.