Dijital Saat Uygulamasının Nexys 4 Kartı Üzerinde Gerçeklenmesi

Posted in FPGA Uygulamaları, Yazılar by Mehmet Ali Çavuşlu On Temmuz 20, 2016. 1 Comment

Aşağıda ayarlanabilir dijital saat uygulamasının Nexys 4 kartı üzerinde gerçeklenmesine ait kodlar ve videolar gösterilmiştir. digital_clock.vhd dosyası saat kontrol işlemlerinin yapıldığı ana modüldür. Saniye ve dakika ayarları için min_sec_digit_cntrl.vhd modülü tasarlanmıştır. Saat ayarları için ise hour_digit_cntrl.vhd modülü tasarlanmıştır.

Digital Saat tasarımında her bir birimin ayarlanabilmesi sağlanmıştır. Saatin çalışmasına ilişkin video aşağıdadır.

Source code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 
entity digital_clock is
    generic(
        SYS_FREQ : integer := 100_000_000
    );
    Port( 
        in_clk : in std_logic;
        in_rst : in std_logic;
        in_set : in std_logic;
        in_chng_seg : in std_logic;
        in_inc : in std_logic;
        out_seg : out std_logic_vector(7 downto 0);
        out_seg_leds : out std_logic_vector(7 downto 0)          
    );
end digital_clock;
 
architecture Behavioral of digital_clock is
 
 
    component hour_digit_cntrl 
    Port ( 
        in_clk : in std_logic;
        in_rst : in std_logic;
        in_pulse : in std_logic;
        in_inc_right : in std_logic;
        in_inc_left : in std_logic;
        out_right_digit : out std_logic_vector(3 downto 0);
        out_left_digit : out std_logic_vector(3 downto 0)
    );
    end component;
    
    component min_sec_digit_cntrl
    Generic(
        DIGIT_SIZE : integer := 10
    );
    Port ( 
        in_clk : in std_logic;
        in_rst : in std_logic;
        in_pulse : in std_logic;
        in_inc : in std_logic;
        out_digit : out std_logic_vector(3 downto 0);
        out_pulse : out std_logic       
    );  
    end component;
    
    component bcd2seven_segment
    Port ( 
        in_bcd : in std_logic_vector(3 downto 0);
        out_seven_segment : out std_logic_vector(7 downto 0)
    );
    end component;
    
    component pulse_generator
    generic(
        FREQ : integer := 100_000_000
    );
    Port ( 
        in_clk : in std_logic;
        in_rst : in std_logic;
        out_sec_pulse : out std_logic
    );
    end component;
    
    type t_Time_Digits is array (0 to 5) of std_logic_vector(3 downto 0);
    signal r_Time_Digits : t_Time_Digits := (others=>(others => '0'));
    
    signal r_bcd : std_logic_vector(3 downto 0) := (others => '0');
    signal r_seg_leds : std_logic_vector(7 downto 0) := (others => '0');
    signal r_seg : std_logic_vector(5 downto 0) := "011111"; 
    signal r_seg_cnt : std_logic_vector(2 downto 0) := (others => '0');
    signal r_seg_pulse : std_logic := '0';
    --
    signal r_sec_pulse : std_logic := '0';
    signal r_sec_right_pulse : std_logic := '0';
    signal r_sec_left_pulse : std_logic := '0';
    signal r_min_right_pulse : std_logic := '0';
    signal r_min_left_pulse : std_logic := '0'; 
    --
    signal r_set : std_logic := '0';
    signal r_set_chk : std_logic_vector(5 downto 0) := "011111"; 
    signal r_set_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
    signal r_set_cnt : integer := 0;
    signal r_set_stts : std_logic := '0';
    
    
    signal r_chng_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
    signal r_set_seg : std_logic_vector(2 downto 0) := (others=> '0');
    
    signal r_inc_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
    signal r_inc_seg : std_logic_vector(5 downto 0) := (others=> '0');
    
    function f_set_shift(r_seg : std_logic_vector(5 downto 0) ; r_set_stts : std_logic; r_set_seg : std_logic_vector(2 downto 0) ) return std_logic_vector is
        variable v_seg : std_logic_vector(5 downto 0);
    begin
        v_seg := r_seg;
        if v_seg(conv_integer(r_set_seg)) = '0' then
            v_seg(conv_integer(r_set_seg)) := r_set_stts;
        end if;
        return ("11" & v_seg);
    end f_set_shift;
 
begin
 
    out_seg_leds <= r_seg_leds;
    out_seg <= f_set_shift(r_seg, r_set_stts, r_set_seg);
    
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_set_cnt <= 0;
            r_set_stts <= '0';
        elsif rising_edge(in_clk) then
            if r_set = '1' then
                if r_set_cnt = (SYS_FREQ / 2) - 1 then
                    r_set_cnt <= 0;
                    r_set_stts <= not r_set_stts;
                else
                    r_set_cnt <= r_set_cnt + 1;
                end if;
            else
                r_set_cnt <= 0;
                r_set_stts <= '0';
            end if;
        end if; 
    end process;
    
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_inc_seg <= (others => '0');
        elsif rising_edge(in_clk) then
            r_inc_seg <= (others => '0');
            if r_inc_cntrl(2 downto 1) = "01" then
                r_inc_seg(5 - conv_integer(r_set_seg)) <= '1';
            end if;             
        end if;
    end process;        
        
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then            
            r_inc_cntrl <= (others=> '0');
        elsif rising_edge(in_clk) then
            r_inc_cntrl <= r_inc_cntrl(1 downto 0) &  in_inc;
        end if;
    end process;
    
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_seg <= "011111";
            r_set_chk <= "111111";  
        elsif rising_edge(in_clk) then
            if r_seg_pulse = '1' then
                r_seg <= r_seg(4 downto 0) & r_seg(5);
 
            end if;         
        end if;
    end process;
 
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_set_seg <= (others => '0');
        elsif rising_edge(in_clk) then
            if r_chng_cntrl(2 downto 1) = "01" then
                if r_set_seg = 5 then
                    r_set_seg <= (others => '0');
                else
                    r_set_seg <= r_set_seg + 1;
                end if;
            end if;             
        end if;
    end process;        
        
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then            
            r_chng_cntrl <= (others=> '0');
        elsif rising_edge(in_clk) then
            r_chng_cntrl <= r_chng_cntrl(1 downto 0) &  in_chng_seg;
        end if;
    end process;    
    
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_seg_cnt <= (others => '0');
            r_bcd <= (others => '0'); 
                
        elsif rising_edge(in_clk) then
            if r_seg_pulse = '1' then
                r_bcd <= r_Time_Digits(5 - conv_integer(r_seg_cnt));
                if r_seg_cnt = 5 then
                    r_seg_cnt <= (others => '0');
                else
                    r_seg_cnt <= r_seg_cnt + 1;
                end if;
            end if;         
        end if;
    end process;
    
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_set <= '0';
        elsif rising_edge(in_clk) then
            if r_set_cntrl(2 downto 1) = "01" then
                r_set <= not r_set;
            end if;             
        end if;
    end process;        
        
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then            
            r_set_cntrl <= (others=> '0');
        elsif rising_edge(in_clk) then
            r_set_cntrl <= r_set_cntrl(1 downto 0) &  in_set;
        end if;
    end process;    
    
    
    bcd2seven_segment_map : bcd2seven_segment 
    Port  map( 
        in_bcd => r_bcd, 
        out_seven_segment => r_seg_leds
    );
 
    hour_digit_cntrl_map : hour_digit_cntrl
    Port map ( 
        in_clk => in_clk, 
        in_rst => in_rst,
        in_pulse => r_min_left_pulse,
        in_inc_right => r_inc_seg(1),
        in_inc_left => r_inc_seg(0),
        out_right_digit => r_Time_Digits(1),
        out_left_digit => r_Time_Digits(0)
    );
    
    min_left_digit : min_sec_digit_cntrl
    Generic map(
        DIGIT_SIZE => 6
    )
    Port map( 
        in_clk => in_clk, 
        in_rst => in_rst,
        in_pulse => r_min_right_pulse,
        in_inc => r_inc_seg(2),
        out_digit => r_Time_Digits(2),
        out_pulse => r_min_left_pulse
    );  
 
    min_right_digit : min_sec_digit_cntrl
    Generic map(
        DIGIT_SIZE => 10
    )
    Port map( 
        in_clk => in_clk, 
        in_rst => in_rst,
        in_pulse => r_sec_left_pulse,
        in_inc => r_inc_seg(3),
        out_digit => r_Time_Digits(3),
        out_pulse => r_min_right_pulse
    );  
 
    sec_left_digit : min_sec_digit_cntrl
    Generic map(
        DIGIT_SIZE => 6
    )
    Port map( 
        in_clk => in_clk, 
        in_rst => in_rst,
        in_pulse => r_sec_right_pulse,
        in_inc => r_inc_seg(4),
        out_digit => r_Time_Digits(4),
        out_pulse => r_sec_left_pulse
    );  
 
    sec_right_digit : min_sec_digit_cntrl
    Generic map(
        DIGIT_SIZE => 10
    )
    Port map( 
        in_clk => in_clk, 
        in_rst => in_rst,
        in_pulse => r_sec_pulse,
        in_inc => r_inc_seg(5),
        out_digit => r_Time_Digits(5),
        out_pulse => r_sec_right_pulse
    );  
    
    seg_pulse_map : pulse_generator
    generic map(
        FREQ => 10_000
    )
    Port map ( 
        in_clk => in_clk,
        in_rst => in_rst,
        out_sec_pulse => r_seg_pulse
    );  
    
    one_second_pulse_map : pulse_generator
    generic map(
        FREQ => SYS_FREQ
    )
    Port map ( 
        in_clk => in_clk,
        in_rst => in_rst,
        out_sec_pulse => r_sec_pulse
    );
 
end Behavioral;

Source code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity pulse_generator is
    generic(
        FREQ : integer := 100_000_000
    );
    Port ( 
        in_clk : in std_logic;
        in_rst : in std_logic;
        out_sec_pulse : out std_logic
    );
end pulse_generator;
 
architecture Behavioral of pulse_generator is
 
    signal r_sec_pulse : std_logic := '0';
    signal r_cnt : integer := 0;
    
begin
 
    out_sec_pulse <= r_sec_pulse;
 
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_cnt<= 0;
            r_sec_pulse <= '0';
            
        elsif rising_edge(in_clk) then
            if r_cnt = FREQ - 1 then
                r_sec_pulse <= '1';
                r_cnt<= 0;
            else
                r_sec_pulse <= '0';
                r_cnt <= r_cnt + 1;         
            end if;
            
        end if;
    end process;
 
end Behavioral;

Source code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 
entity min_sec_digit_cntrl is
    Generic(
        DIGIT_SIZE : integer := 10
    );
    Port ( 
        in_clk : in std_logic;
        in_rst : in std_logic;
        in_pulse : in std_logic;
        in_inc : in std_logic;
        out_digit : out std_logic_vector(3 downto 0);
        out_pulse : out std_logic   
    );
end min_sec_digit_cntrl;
 
architecture Behavioral of min_sec_digit_cntrl is
 
    signal r_digit : std_logic_vector(3 downto 0) := (others => '0');
    signal r_pulse : std_logic := '0';
 
begin
 
    out_digit <= r_digit;
    out_pulse <= r_pulse;
    
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_digit <= (others => '0');
            r_pulse <= '0';
        elsif rising_edge(in_clk) then
            r_pulse <= '0';
            if in_pulse = '1' then
                if r_digit = DIGIT_SIZE - 1 then
                    r_pulse <= '1';
                    r_digit <= (others => '0');
                else
                    r_digit <= r_digit + 1;
                end if;                             
            end if;
            
            if in_inc = '1' then
                if r_digit = DIGIT_SIZE - 1 then
                    r_digit <= (others => '0');
                else
                    r_digit <= r_digit + 1;
                end if; 
            end if;
        end if;
    end process;
 
end Behavioral;

Source code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 
entity hour_digit_cntrl is
    Port ( 
        in_clk : in std_logic;
        in_rst : in std_logic;
        in_pulse : in std_logic;
        in_inc_right : in std_logic;
        in_inc_left : in std_logic;
        out_right_digit : out std_logic_vector(3 downto 0);
        out_left_digit : out std_logic_vector(3 downto 0)
    );
end hour_digit_cntrl;
 
architecture Behavioral of hour_digit_cntrl is
 
    signal r_right_digit : std_logic_vector(3 downto 0);
    signal r_left_digit : std_logic_vector(3 downto 0);
 
begin
    
    out_right_digit <= r_right_digit;
    out_left_digit <= r_left_digit;
 
    process(in_clk, in_rst)
    begin
        if in_rst = '1' then
            r_right_digit <= (others => '0');
            r_left_digit <= (others => '0');
        elsif rising_edge(in_clk) then
            if in_pulse = '1' then
                if (r_left_digit /= 2 and r_right_digit = 9) or 
                    (r_left_digit = 2 and r_right_digit = 3) then       
                    r_right_digit <= (others => '0');
                    if r_left_digit = 2 then
                        r_left_digit <= (others => '0');
                    else
                        r_left_digit <= r_left_digit + 1;
                    end if;
                else
                    r_right_digit <= r_right_digit + 1;
                end if;                             
            end if;
            
            if in_inc_right = '1' then
                if (r_left_digit /= 2 and r_right_digit = 9) or 
                    (r_left_digit = 2 and r_right_digit = 3) then       
                    r_right_digit <= (others => '0');
                else
                    r_right_digit <= r_right_digit + 1;
                end if; 
            end if;
            
            if in_inc_left = '1' then
                if r_left_digit = 2 then
                    r_left_digit <= (others => '0');
                else
                    r_left_digit <= r_left_digit + 1;
                end if;
            end if;
        end if;
    end process;
 
 
end Behavioral;

Source code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity bcd2seven_segment is
    Port ( 
        in_bcd : in std_logic_vector(3 downto 0);
        out_seven_segment : out std_logic_vector(7 downto 0)
    );
end bcd2seven_segment;
 
architecture Behavioral of bcd2seven_segment is
 
    signal r_seven_segment : std_logic_vector(7 downto 0) := (others => '0');
 
begin
 
    out_seven_segment <= r_seven_segment;
 
    process(in_bcd)
    begin
        case in_bcd is
            when "0000" => 
                r_seven_segment <= "10000001";
            when "0001" => 
                r_seven_segment <= "11001111";              
            when "0010" => 
                r_seven_segment <= "10010010";              
            when "0011" => 
                r_seven_segment <= "10000110";              
            when "0100" => 
                r_seven_segment <= "11001100";              
            when "0101" => 
                r_seven_segment <= "10100100";
            when "0110" => 
                r_seven_segment <= "10100000";
            when "0111" => 
                r_seven_segment <= "10001111";
            when "1000" => 
                r_seven_segment <= "10000000";
            when "1001" => 
                r_seven_segment <= "10000100";
            when others => 
                r_seven_segment <= "00000000";          
        end case;
    end process;
 
 
end Behavioral;

Source code

set_property PACKAGE_PIN E3 [get_ports in_clk]
set_property IOSTANDARD LVCMOS33 [get_ports in_clk]
 
set_property PACKAGE_PIN F15 [get_ports in_rst]
set_property IOSTANDARD LVCMOS33 [get_ports in_rst]
 
set_property PACKAGE_PIN M1 [get_ports {out_seg[7]}]
set_property PACKAGE_PIN L1 [get_ports {out_seg[6]}]
set_property PACKAGE_PIN N4 [get_ports {out_seg[5]}]
set_property PACKAGE_PIN N2 [get_ports {out_seg[4]}]
set_property PACKAGE_PIN N5 [get_ports {out_seg[3]}]
set_property PACKAGE_PIN M3 [get_ports {out_seg[2]}]
set_property PACKAGE_PIN M6 [get_ports {out_seg[1]}]
set_property PACKAGE_PIN N6 [get_ports {out_seg[0]}]
 
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg[0]}]
 
 
set_property PACKAGE_PIN M4 [get_ports {out_seg_leds[7]}]
set_property PACKAGE_PIN L3 [get_ports {out_seg_leds[6]}]
set_property PACKAGE_PIN N1 [get_ports {out_seg_leds[5]}]
set_property PACKAGE_PIN L5 [get_ports {out_seg_leds[4]}]
set_property PACKAGE_PIN L4 [get_ports {out_seg_leds[3]}]
set_property PACKAGE_PIN K3 [get_ports {out_seg_leds[2]}]
set_property PACKAGE_PIN M2 [get_ports {out_seg_leds[1]}]
set_property PACKAGE_PIN L6 [get_ports {out_seg_leds[0]}]
 
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_seg_leds[0]}]
 
 
set_property PACKAGE_PIN E16 [get_ports in_set]
set_property PACKAGE_PIN R10 [get_ports in_inc]
set_property IOSTANDARD LVCMOS33 [get_ports in_inc]
set_property IOSTANDARD LVCMOS33 [get_ports in_set]
 
set_property PACKAGE_PIN V10 [get_ports in_chng_seg]
set_property IOSTANDARD LVCMOS33 [get_ports in_chng_seg]

Latest Comments

Temmuz 22, 2016

Rusen Temmuz 20, 2016

Helal m ali istersen yapamayacagin birsey yok.