Nexys 4 Kartı kullanarak PWM ile Sinüs Üretme
Aşağıda Nexys 4 karıt üzerinde PWM kullanarak sinüs üreten VHDL kodu verilmiştir.
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- use IEEE.MATH_REAL.ALL;
- entity pwm is
- generic(
- SISTEM_FREKANSI : integer := 100_000_000;
- COZUNURLUK : integer := 16;
- ORNEK_SAYISI : integer := 128
- );
- Port(
- in_clk : in std_logic;
- in_rst : in std_logic;
- out_data : out std_logic
- );
- end pwm;
- architecture Behavioral of pwm is
- type t_Veri_Tablosu is array (0 to ORNEK_SAYISI - 1) of integer;
- -- range 0 to COZUNURLUK;
- constant MAX_FREKANS : integer :=
- SISTEM_FREKANSI / (COZUNURLUK * ORNEK_SAYISI);
- function f_Veri_Olusturma(COZUNURLUK, ORNEK_SAYISI : integer)
- return t_Veri_Tablosu is
- variable v_Veri_Tablosu : t_Veri_Tablosu;
- begin
- for n_i in 0 to ORNEK_SAYISI - 1 loop
- v_Veri_Tablosu(n_i) := integer(real(COZUNURLUK/ 2 )
- + real((COZUNURLUK-1)/ 2) *
- sin(real(n_i) / real(ORNEK_SAYISI) * 1.0 * 2.0 * MATH_PI));
- end loop;
- return v_Veri_Tablosu;
- end f_Veri_Olusturma;
- constant c_Veri_Tablosu : t_Veri_Tablosu :=
- f_Veri_Olusturma(COZUNURLUK, ORNEK_SAYISI);
- signal r_cnt : integer range 0 to COZUNURLUK;
- signal r_data_cnt : integer range 0 to ORNEK_SAYISI - 1;
- signal r_clk_cnt : std_logic_vector(3 downto 0);
- signal r_clk : std_logic;
- begin
- r_clk <= in_clk;--r_clk_cnt(r_clk_cnt'high);
- process(r_clk, in_rst)
- begin
- if in_rst = '1' then
- r_cnt <= 0;
- elsif rising_edge(r_clk) then
- if r_cnt = COZUNURLUK - 1 then
- r_cnt <= 0;
- else
- r_cnt <= r_cnt + 1;
- end if;
- end if;
- end process;
- process(r_clk, in_rst)
- begin
- if in_rst = '1' then
- r_data_cnt <= 0;
- elsif rising_edge(r_clk) then
- if r_cnt = COZUNURLUK - 1 then
- if r_data_cnt = ORNEK_SAYISI - 1 then
- r_data_cnt <= 0;
- else
- r_data_cnt <= r_data_cnt + 1;
- end if;
- end if;
- end if;
- end process;
- process(r_clk)
- begin
- if rising_edge(r_clk) then
- if r_cnt < c_Veri_Tablosu(r_data_cnt) then
- out_data <= '0';
- else
- out_data <= '1';
- end if;
- end if;
- end procesS;
- end Behavioral;